A sample and hold circuit for pipelined ADC

A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.