Ternary logic circuit design based on single electron transistors

被引:0
|
作者
吴刚 [1 ]
蔡理 [1 ]
李芹 [1 ]
机构
[1] Institute of Science,Air Force Engineering University
关键词
single electron transistor; adjustable threshold voltage; ternary logic;
D O I
暂无
中图分类号
TN791 [];
学科分类号
080902 ;
摘要
Based on the I–V characteristics and the function of adjustable threshold voltage of a single electron transistor (SET),we design the basic ternary logic circuits,which have been simulated by SPICE and their power and transient characteristics have been extensively analyzed. The simulation results indicate that the proposed circuits exhibit a simpler structure,smaller signal delay and lower power.
引用
收藏
页码:96 / 100
页数:5
相关论文
共 50 条
  • [21] Macromodeling of single-electron transistors for efficient circuit simulation
    Yu, YS
    Hwang, SW
    Ahn, D
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (08) : 1667 - 1671
  • [22] TERNARY LOGIC BASED ON A NOVEL MOS BUILDING BLOCK CIRCUIT
    AYTAC, HM
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1987, 63 (02) : 241 - 251
  • [23] A Novel Comparator Circuit of Single-electron and MOS Transistors
    Zhou, Youjie
    Xiong, Chunhua
    Lu, Changbo
    PRODUCT DESIGN AND MANUFACTURE, 2012, 120 : 516 - 519
  • [24] Design of New Logic Architectures Utilizing Optimized Suspended-Gate Single-Electron Transistors
    Pruvost, Benjamin
    Uchida, Ken
    Mizuta, Hiroshi
    Oda, Shunri
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2010, 9 (04) : 504 - 512
  • [25] Optically Controlled Ternary Logic Circuits Based on Organic Antiambipolar Transistors
    Panigrahi, Debdatta
    Hayakawa, Ryoma
    Fuchii, Kota
    Yamada, Yoichi
    Wakayama, Yutaka
    ADVANCED ELECTRONIC MATERIALS, 2021, 7 (01)
  • [26] Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
    Schmid, A
    Leblebici, Y
    2003 THIRD IEEE CONFERENCE ON NANOTECHNOLOGY, VOLS ONE AND TWO, PROCEEDINGS, 2003, : 516 - 519
  • [27] Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
    Schmid, A
    Leblebici, Y
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (11) : 1156 - 1166
  • [28] Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
    Lee, Dong Seup
    Yang, Hong-Seon
    Kang, Kwon-Chil
    Lee, Joung-Eob
    Lee, Jung Han
    Park, Sang Hyuk
    Park, Byung-Gook
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2009, 48 (07)
  • [29] CNTFET-based logic circuit design
    O'Connor, I.
    Liu, J.
    Gaffiot, F.
    IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 46 - 51
  • [30] Reconfigurable Boolean Logic Using Magnetic Single-Electron Transistors
    Gonzalez-Zalba, M. Fernando
    Ciccarelli, Chiara
    Zarbo, Liviu P.
    Irvine, Andrew C.
    Campion, Richard C.
    Gallagher, Bryan L.
    Jungwirth, Tomas
    Ferguson, Andrew J.
    Wunderlich, Joerg
    PLOS ONE, 2015, 10 (04):