LSB page refresh based retention error recovery scheme for MLC NAND Flash

被引：0
|
作者：
Haozhi MA [1 ]
Lifang LIU [1 ]
Liyang PAN [1 ,2 ]
Jun XU [1 ,2 ]
机构：
[1] Institute of Microelectronics, Tsinghua University
[2] Tsinghua National Laboratory for Information Science and Technology
来源：
Science China(Information Sciences) | 2016年 / 59卷 / 04期
基金：
中国国家自然科学基金;
关键词：
NAND flash; reliability; retention; refresh; data error recovery;
D O I：
暂无
中图分类号：
TP333 [存贮器];
学科分类号：
081201 ;
摘要：
NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell(MLC) technology. High retention error rate in highly program/erase(P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit(LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.
引用
收藏
页码：121 / 131
页数：11
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