LSB page refresh based retention error recovery scheme for MLC NAND Flash

被引：0
|
作者：
Haozhi MA [1 ]
Lifang LIU [1 ]
Liyang PAN [1 ,2 ]
Jun XU [1 ,2 ]
机构：
[1] Institute of Microelectronics, Tsinghua University
[2] Tsinghua National Laboratory for Information Science and Technology
来源：
Science China(Information Sciences) | 2016年 / 59卷 / 04期
基金：
中国国家自然科学基金;
关键词：
NAND flash; reliability; retention; refresh; data error recovery;
D O I：
暂无
中图分类号：
TP333 [存贮器];
学科分类号：
081201 ;
摘要：
NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell(MLC) technology. High retention error rate in highly program/erase(P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit(LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.
引用
收藏
页码：121 / 131
页数：11
相关论文
共 50 条
  • [1] LSB page refresh based retention error recovery scheme for MLC NAND Flash
    Haozhi Ma
    Lifang Liu
    Liyang Pan
    Jun Xu
    [J]. Science China Information Sciences, 2016, 59
  • [2] LSB page refresh based retention error recovery scheme for MLC NAND Flash
    Ma, Haozhi
    Liu, Lifang
    Pan, Liyang
    Xu, Jun
    [J]. SCIENCE CHINA-INFORMATION SCIENCES, 2016, 59 (04)
  • [3] MLC Nand Flash Retention Error Recovery Scheme Through Word Line Program Disturbance
    Ma, Haozhi
    Zou, Hongfei
    Pan, Liyang
    Xu, Jun
    [J]. 2014 INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE), 2014,
  • [4] A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory
    Wei, Debao
    Deng, Libao
    Hao, Mengqi
    Qiao, Liyan
    Peng, Xiyuan
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2018, 60 : 65 - 76
  • [5] Word line program disturbance based data retention error recovery strategy for MLC NAND Flash
    Ma, Haozhi
    Pan, Liyang
    Song, Changlai
    Gao, Zhongyi
    Wu, Dong
    Xu, Jun
    [J]. SOLID-STATE ELECTRONICS, 2015, 109 : 1 - 7
  • [6] Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory
    Lee, Jaeil
    Shin, Dongkun
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (07) : 1110 - 1114
  • [7] Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery
    Cai, Yu
    Luo, Yixin
    Haratsch, Erich F.
    Mai, Ken
    Mutlu, Onur
    [J]. 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, : 551 - 563
  • [8] A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories
    Park, Ki-Tae
    Kang, Myounggon
    Kim, Doogon
    Hwang, Soon-Wook
    Choi, Byung Yong
    Lee, Yeong-Taek
    Kim, Changhyun
    Kim, Kinam
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) : 919 - 928
  • [9] Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding
    Chengen Yang
    Hsing-Min Chen
    Trevor N. Mudge
    Chaitali Chakrabarti
    [J]. Journal of Signal Processing Systems, 2014, 76 : 225 - 234
  • [10] Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding
    Yang, Chengen
    Chen, Hsing-Min
    Mudge, Trevor N.
    Chakrabarti, Chaitali
    [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2014, 76 (03): : 225 - 234
12345