共 50 条
- [41] Design of low-power double-edge triggered flip-flop 2005 6th International Conference on ASIC Proceedings, Books 1 and 2, 2005, : 126 - 127
- [42] An explicit-pulsed double-edge triggered JK flip-flop 2009 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS AND SIGNAL PROCESSING (WCSP 2009), 2009, : 1399 - 1402
- [45] Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop Journal of Electronic Testing, 2013, 29 : 545 - 554
- [46] A low-swing clock double-edge triggered flip-flop 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 183 - 186
- [47] Resonant Tunneling Diode based QMOS edge triggered flip-flop design 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS, 2004, : 705 - 708
- [48] Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2013, 29 (04): : 545 - 554
- [50] CONSTRUCTIONS OF TERNARY FLIP-FLOP CIRCUITS. Systems, computers, controls, 1984, 15 (03): : 1 - 9