Device parameter optimization for sub-20nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate(HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated.The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure.The punch through stop layer(PTSL) and source drain extension(SDE) doping profiles are carefully optimized.The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation.The band-edged MG has a better short channel effect immunity,but the lower effective work function(EWF) MG shows a larger driveability.A tradeoff choice for different EWF MGs should be carefully designed for the device’s scaling.