Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

被引:0
|
作者
王文廉 [1 ,2 ]
张波 [2 ]
李肇基 [2 ]
机构
[1] State Key Laboratory of Electronic Measurement Technology,North University of China
[2] State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China
基金
中国国家自然科学基金;
关键词
super junction; LDMOS; substrate-assisted depletion effect;
D O I
暂无
中图分类号
TN386.1 [金属-氧化物-半导体(MOS)器件];
学科分类号
0805 ; 080501 ; 080502 ; 080903 ;
摘要
The lateral super junction(SJ) power devices suffer the substrate-assisted depletion(SAD) effect,which breaks the charge balance of SJ resulting in the low breakdown voltage(BV).A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS).High density interface charges enhance the electric field in the buried oxide(BOX) layer to increase the block voltage of BOX,which suppresses the SAD effect to achieve the charge balance of SJ.In order to obtain the linear enhancement of electric field,SOI SJ-LDMOS with trenched BOX is presented.Because the trenched BOX self-adaptively collects holes according to the variable electric field strength,the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need.As a result,the charge balance between N and P pillars of SJ is achieved,which improves the BV of SJ-LDMOS to close that of the idea SJ structure.
引用
收藏
页码:28 / 32
页数:5
相关论文
共 50 条
  • [21] A breakdown model of LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology
    Dong, Ziming
    Duan, Baoxing
    Li, Mingzhe
    Wang, YanDong
    Yang, Yintang
    SOLID-STATE ELECTRONICS, 2020, 166
  • [22] High-Voltage SOI Deep Trench LDMOS with Quasi Vertical Super Junction Structure
    Zhang, Jinping
    Zou, Hua
    Zhao, Qian
    Wang, Kang
    Li, Zehong
    Li, Zhaoji
    Zhang, Bo
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 332 - 334
  • [23] Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor
    Wu, Lijuan
    Ding, Qilin
    Chen, Jiaqi
    SILICON, 2021, 13 (10) : 3441 - 3446
  • [24] Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage
    Luo, Xiaorong
    Wei, Jie
    Shi, Xianlong
    Zhou, Kun
    Tian, Ruichao
    Zhang, Bo
    Li, Zhaoji
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (12) : 4304 - 4308
  • [25] Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor
    Lijuan Wu
    Qilin Ding
    Jiaqi Chen
    Silicon, 2021, 13 : 3441 - 3446
  • [26] Breakdown characteristics of SOI LDMOS high voltage devices with variable low k dielectric laye
    IC Design Center, University of Electronic Science and Technology, Chengdu 610054, China
    Pan Tao Ti Hsueh Pao, 2006, 5 (881-885):
  • [27] Super junction LDMOS with P-trench and stepped buried oxide layer for high performance
    Tang, Pan-pan
    Wang, Ying
    Cao, Fei
    Yu, Cheng-hao
    Bao, Meng-tian
    Luo, Xin
    SUPERLATTICES AND MICROSTRUCTURES, 2019, 125 : 198 - 204
  • [28] New REBULF super junction LDMOS with the N type buffered layer
    Duan Bao-Xing
    Cao Zhen
    Yuan Xiao-Ning
    Yang Yin-Tang
    ACTA PHYSICA SINICA, 2014, 63 (22)
  • [29] BREAKDOWN VOLTAGE IN LDMOS TRANSISTORS USING INTERNAL FIELD RINGS
    NEZAR, A
    SALAMA, CAT
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (07) : 1676 - 1680
  • [30] A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage
    Xiang, Zhenyu
    Lin, Yonghui
    Zhang, Chunwei
    Guo, Haijun
    Li, Yang
    Yue, Wenjing
    Gao, Song
    Kan, Hao
    SOLID-STATE ELECTRONICS, 2022, 189