A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

被引：0

作者：

马飞 ^{[1
]}

刘红侠 ^{[1
]}

匡潜玮 ^{[1
]}

樊继斌 ^{[1
]}

机构：

[1] Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Material and Devices,School of Microelectronics,Xidian University

来源：

Chinese Physics B | 2012年 / 05期

基金：

中央高校基本科研业务费专项资金资助; 中国国家自然科学基金;

关键词：

threshold voltage; high-k gate dielectric; fringing-induced barrier lowering; short channel effect;

D O I：

暂无

中图分类号：

TN386.1 [金属-氧化物-半导体（MOS）器件];

学科分类号：

0805 ; 080501 ; 080502 ; 080903 ;

摘要：

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.

引用

页码：600 / 605

页数：6

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