Novel approach to reduce the pattern effect in 10-Gb/s clock recovery

被引：1
|
作者：
王桐
娄采云
霍力
高以智
机构：
[1] Beijing 100084
[2] Department of Electronic Engineering
[3] Tsinghua University
来源：
ChineseOpticsLetters | 2004年 / 02期
基金：
中国国家自然科学基金;
关键词：
口口; STD; MA; data; SOA;
D O I：
暂无
中图分类号：
TN915 [通信网];
学科分类号：
摘要：
A Fabry-Perot (F-P) etalon and a semiconductor optical amplifier (SOA) were combined to preprocess the data signals before clock recovery. With this technology in the 10-Gb/s clock recovery utilizing injection mode-locked laser (IMLL) based on SOA, the amplitude fluctuation and timing jitters caused by the pattern effect in recovered clock pulses were greatly reduced, experimentally. It also demonstrated that clock could be recovered from the very degraded signals.
引用
收藏
页码：69 / 71
页数：3
相关论文
共 50 条
  • [1] A 10-gb/s CMOS clock and data recovery circuit
    Savoj, J
    Razavi, B
    2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, : 136 - 139
  • [2] Optical clock recovery from 10-Gb/s NRZ signal
    Betti, S
    Bulli, C
    Curti, F
    Duca, E
    Persia, S
    Reale, A
    Tosi-Beleffi, GM
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2004, 42 (06) : 435 - 437
  • [3] Clock and data recovery circuit for 10-Gb/s asynchronous optical packets
    Kanellos, GT
    Stampoulidis, L
    Pleros, N
    Houbavlis, T
    Tsiokos, D
    Kehayas, E
    Avramopoulos, H
    Guekos, G
    IEEE PHOTONICS TECHNOLOGY LETTERS, 2003, 15 (11) : 1666 - 1668
  • [4] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
    Kreienkamp, R
    Langmann, U
    Zimmermann, C
    Aoyama, T
    PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 73 - 76
  • [5] A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
    Kreienkamp, R
    Langmann, U
    Zimmermann, C
    Aoyama, T
    Siedhoff, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (03) : 736 - 743
  • [6] A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator
    Nosaka, H
    Ishii, K
    Enoki, T
    Shibata, T
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (02) : 192 - 197
  • [7] Experimental Demonstration of a Novel 5/10-Gb/s Burst-Mode Clock and Data Recovery Circuit for Gigabit PONs
    Zeng, Ming
    Shastri, Bhavin J.
    Zicha, Nicholas
    Plant, David V.
    OFC: 2009 CONFERENCE ON OPTICAL FIBER COMMUNICATION, VOLS 1-5, 2009, : 2364 - 2366
  • [8] Equalization and clock and data recovery techniques for 10-gb/s CMOS serial-link receivers
    Gondi, Srikanth
    Razavi, Behzad
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (09) : 1999 - 2011
  • [9] SiGeBiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems
    Meghelli, M
    Parker, B
    Ainspan, H
    Soyuer, M
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) : 1992 - 1995
  • [10] A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
    Rhee, W
    Ainspan, H
    Rylov, S
    Rylyakov, A
    Beakes, M
    Friedman, D
    Gowda, S
    Soyuer, M
    PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, : 81 - 84
12345