Redundancy based Resistor String DAC with an all digital calibration algorithm

被引：0

作者：

Bruce, Isaac ^{[1
]}

Darko, Emmanuel Nti ^{[1
]}

Odion, Ekaniyere Oko ^{[1
]}

Crabb, Matthew ^{[1
]}

Chen, Degang ^{[1
]}

机构：

[1] Iowa State Univ, Ames, IA 50011 USA

来源：

2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 | 2024年

关键词：

sub-radix; digital-to-analog converter (DAC); matching; string DAC; Integral Non-linearity (INL);

D O I：

10.1109/MWSCAS60917.2024.10658819

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel 3-segment interpolating resistor string ladder DAC with sub-radix/redundancy characteristics in the DAC transfer curve. A simple all-digital calibration algorithm is presented which trades off resolution for linearity. The design is shown to reduce the area overhead significantly compared to the conventional resistor string DAC. A 15-bit version of the DAC using poly-resistors is designed in the TSMC 180nm process and the calibration algorithm implemented in MATLAB to obtain a 13-bit linear DAC with a worst case INL of 0.78LSBs across 100 Monte-Carlo iterations with resistor matching at only the 5-bit level.

引用

页码：571 / 575

页数：5

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