Creative and accurate method for optimal hardware implementation of neurons and biological cells: Application in FPGA-based implementation of cardiac pacemaker cell

被引:1
|
作者
Ghanbarpour, Gilda [1 ]
Ghanbarpour, Milad [2 ]
Spari, Pourya [3 ]
机构
[1] Razi Univ, Dept Comp Engn, Kermanshah, Iran
[2] Kermanshah Univ Technol, Energy Fac, Dept Elect Engn, Kermanshah, Iran
[3] Razi Univ, Dept Elect Engn, Kermanshah, Iran
关键词
Heart pace maker; Sinoatrial node; Yanagihara-Noma-Irisawa (YNI) model; FPGA; Digital implementation; SPIKING NEURONS; MODELS; REALIZATION;
D O I
10.1016/j.aeue.2024.155561
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The sinoatrial (SA) node cells playa vital role as the principal pacemaker in mammalian hearts, generating regular and spontaneous action potentials to regulate the heart's rhythm. Comprehending the intricate activity of the SA node's operation necessitates a collection of differential formulas that tackle non-linear functions. The study presents anew technique to improve the digital representation of the SA node cell model, offering benefits such as decreased hardware needs, enhanced processing speed and accuracy, and reduced implementation expenses by transforming the original model's differential equations into a unified trigonometric function. This transformation significantly simplifies the computational complexity by eliminating the need for multipliers, resulting in a streamlined set of mathematical expressions. The digital implementation of this novel method can be efficiently realized using the Coordinate Rotation Digital Computer (CORDIC) algorithm, which circumvents the necessity for cumbersome mathematical operations. To demonstrate the viability of this approach, the proposed model is successfully synthesized and implemented on a Field-Programmable Gate Array (FPGA). The results of the implementation demonstrate a significant rise in the operating frequency, which is approximately 6.14 times greater than that of the original model. Furthermore, there is a notable 45 percent decrease in power usage. The lowered hardware needs make significant scalability possible, thus allowing for the inclusion of approximately 12 times as many SA node cells on a sole FPGA board in comparison to the original design.
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页数:9
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