Hardware implementation of a background substraction algorithm in FPGA-based platforms

被引：0
|
作者：
Calvo-Gallego, Elisa [1 ]
Sanchez-Solano, Santiago [1 ]
Brox Jimenez, Piedad [2 ]
机构：
[1] Univ Seville, Inst Microelect Sevilla IMSE CNM, CSIC, Seville, Spain
[2] Univ Seville, Dept Elect & Electromagnetism, Inst Microelect Sevilla IMSE CNM, CSIC, Seville, Spain
来源：
2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT) | 2015年
关键词：
background substraction; foreground extraction; hardware implementation; fuzzy logic-based techniques;
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Different strategies for the implementation of a fuzzy logic-based background subtraction algorithm are presented in this paper. The goal of this contribution is to obtain an efficient implementation suitable to be integrated into hardware platforms with limited resources. In order to find an adequate performance-resources trade-off, the design space is explored taken into account several strategies and implementation options. The final implementation is encapsulated within an IP core that has been used in a demonstrator, built on a Spartan-3A-DSP FPGA development board, suitable for processing VGA (640x480P) @ 60 Hz.
引用
收藏
页码：1688 / 1693
页数：6
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