A Low-Dropout Linear Regulator with Nested Miller Compensation in 65-nm SOI CMOS

A low-dropout linear regulator (LDO) with nested Miller compensation using a 65-nm SOI CMOS technology is presented in this paper. A bandgap voltage reference (BGR) with low temperature coefficient (TC) and high power supply rejection ratio (PSRR) is designed. And a two-stage error amplifier (EA) is used in the design. Moreover, nested Miller compensation is presented for the stability of the circuit. The designed BGR and LDO achieve low TCs of 9.832 ppm/degrees C and 13.693 ppm/degrees C from - 55 degrees C to 125 degrees C. The PSRRs of the proposed BGR are - 81.2 dB at 1 kHz, - 80.3 dB at 10 kHz and - 66.6 dB at 100 kHz. In addition, the presented LDO can work under the input voltage of 3.1 V- 6 V with an output voltage of 2.88 V at maximum load current of 40 mA. The designed LDO can provide a stable output voltage, which can be used to provide supply voltage for the front end modules.