Physically Secure Logic Locking With Nanomagnet Logic

被引:0
|
作者
Edwards, Alexander J. [1 ]
Hassan, Naimul [1 ]
Arzate, Jared D. [2 ]
Chin, Alexander N. [1 ]
Bhattacharya, Dhritiman [3 ]
Shihab, Mustafa M. [1 ]
Zhou, Peng [1 ]
Hu, Xuan [1 ]
Atulasimha, Jayasimha
Makris, Yiorgos [1 ]
Friedman, Joseph S. [1 ]
机构
[1] Univ Texas Dallas, Dept Elect & Comp Engn, Richardson, TX 75080 USA
[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
[3] Virginia Commonwealth Univ, Dept Mech & Nucl Engn, Richmond, VA 23284 USA
关键词
Logic; Security; Nonvolatile memory; Integrated circuits; Foundries; Logic gates; Layout; Boolean satisfiability (SAT) attacks; hardware security; logic locking; nanomagnet logic (NML); perpendicular magnetic anisotropy (PMA); physical security; polymorphic logic; satisfiability; RELIABILITY;
D O I
10.1109/TCAD.2024.3434362
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Securing integrated circuits against counterfeiting through logic locking presents the fundamental challenge of protecting a locking key from physical, Boolean satisfiability (SAT)-based, and structural threats. Prior research has mainly focused on enhancing logic locking to thwart SAT-based and structural attacks but overlooked the necessity of robust physical security. Our work introduces a novel approach: a logic locking scheme utilizing the nonvolatile properties of nanomagnet logic (NML) to provide comprehensive protection. Polymorphic NML minority gates along with conventional locking techniques fortify the locking key against SAT-based and structural threats, while a protective shield, inducing strain in the nanomagnets, offers physical security via a self-destruct mechanism. Although the NML system improves physical security and preserves security against SAT-based and structural attacks, it suffers from drawbacks related to limited reliability and speed, which result in a notable security overhead cost. Consequently, we propose a hybrid CMOS/NML logic locking approach in which NML islands are integrated into a predominantly CMOS-based system. This hybrid solution continues to deliver security against physical, SAT-based, and the known structural attacks while minimizing the associated overhead. We evaluate the security of such hybrid systems against conventional and physically enhanced SAT attacks. The hybrid logic systems are found to retain the security against conventional SAT-based attacks. We further find that these hybrid logic systems are also robust to physically enhanced SAT attacks in which the attacker has access to all internal electrical signals. These hybrid logic systems are thus shown to provide security against all known physical attacks as well as SAT-based attacks, with minimal efficiency tradeoffs resulting from the use of emerging technologies.
引用
收藏
页码:105 / 118
页数:14
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