A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS

被引:0
|
作者
Park, Sungjin [1 ,2 ]
Lee, Sunwoo [1 ,2 ]
Park, Jeongwoo [3 ]
Choi, Hyeong-Seok [4 ]
Lee, Kyogu [5 ,6 ]
Jeon, Dongsuk [1 ,2 ]
机构
[1] Seoul Natl Univ, Res Inst Convergence Sci, Dept Intelligence & Informat, Seoul, South Korea
[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul, South Korea
[3] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon 16419, South Korea
[4] ElevenLabs, New York, NY USA
[5] Seoul Natl Univ, Dept Intelligence & Informat, Seoul 08826, South Korea
[6] Seoul Natl Univ, Interdisciplinary Program Artificial Intelligence, Seoul 08826, South Korea
基金
新加坡国家研究基金会;
关键词
Neural networks; Hearing aids; Real-time systems; Convolution; Optimization; Decoding; Computational modeling; Digital hearing aids; multiplier-less processing element (PE); neural network processor; reconfigurable architecture; speech enhancement (SE); PERFORMANCE; DEVICES;
D O I
10.1109/JSSC.2024.3460426
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Speech enhancement (SE) plays a key role in many audio-related applications by removing noise and enhancing the quality of human voice. Recent deep learning-based approaches provide high-quality SE, but real-time processing of those algorithms is challenging in resource-constrained devices due to high computational complexity. In this article, we present an energy-efficient real-time SE processor aimed at hearing aids. To implement high-quality SE with a very limited power budget, various algorithm and hardware optimization techniques are proposed. Our SE algorithm adaptively allocates computational resources to each region in the input feature domain depending on their importance, reducing overall computations by 29.7%. Along with 4-bit channel-wise logarithmic quantization, the processor adopts a reconfigurable multiplier-less processing element (PE) that supports both pre-/post-processing and neural network layers, resulting in a 21.5% area reduction. In addition, the design employs efficient scheduling and input buffering schemes to reduce on-chip memory access by 70.8%. Fabricated in a 28-nm CMOS process, our design consumes only 740 mu W at 2.5 MHz with a total latency of 39.96 ms, satisfying the real-time processing constraints. In addition, our approach demonstrated higher SE quality than prior art in both objective and subjective evaluations.
引用
收藏
页数:14
相关论文
共 50 条
  • [1] Real-Time Implementation of an Efficient Speech Enhancement Algorithm for Digital Hearing Aids
    高杰
    张辉
    胡广书
    TsinghuaScienceandTechnology, 2006, (04) : 475 - 480
  • [2] Smartphone-based Real-time Speech Enhancement for Improving Hearing Aids Speech Perception
    Rao, Yu
    Hao, Yiya
    Panahi, Issa M. S.
    Kehtarnavaz, Nasser
    2016 38TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2016, : 5885 - 5888
  • [3] A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS
    Lee, Sangwan
    Seo, Hyeongmin
    Shin, Wookjin
    Yang, Dongju
    Sung, Gaeryun
    Lee, Sanghun
    Choi, Dong-Ho
    Kwak, Young-Ho
    Won, Soon-Jae
    Song, Ickhyun
    Han, Jaeduk
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024,
  • [4] A 24.1 TOPS/W mixed-signal BNN processor in 28-nm CMOS
    Kim, Hanseul
    Park, Jongmin
    Lee, Hyunbae
    Yang, Hyeokjoon
    Burm, Jinwook
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2024, 111 (08) : 1288 - 1300
  • [5] Error-compensated time integrator in 28-nm CMOS technology
    Ji, Xincun
    Wang, Youhua
    Shen, Mengqi
    Guo, Yufeng
    ELECTRONICS LETTERS, 2020, 56 (16) : 806 - 807
  • [6] An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS
    Guo, Mohan
    Zhao, Dixian
    Wu, Qisong
    Wu, Jiarui
    Li, Diwei
    Zhang, Peng
    IEEE ACCESS, 2023, 11 : 36041 - 36051
  • [7] REAL-TIME SPEECH SYNTHESIS WITH A FAST PROCESSOR
    ABAUZIT, P
    SERIGNAT, JF
    DEGRYSE, D
    ONDE ELECTRIQUE, 1981, 61 (02): : 53 - 60
  • [8] A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOS
    Yoshita, Tomohiro
    Kadomoto, Junichiro
    Irie, Hidetsugu
    2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024, 2024, : 509 - 513
  • [9] Real-Time Multichannel Deep Speech Enhancement in Hearing Aids: Comparing Monaural and Binaural Processing in Complex Acoustic Scenarios
    Westhausen, Nils L.
    Kayser, Hendrik
    Jansen, Theresa
    Meyer, Bernd T.
    IEEE-ACM TRANSACTIONS ON AUDIO SPEECH AND LANGUAGE PROCESSING, 2024, 32 : 4596 - 4606
  • [10] Single Event Transients in 28-nm CMOS Decoders
    Stenin, Vladimir Ya.
    Levin, Konstantin E.
    2016 INTERNATIONAL SIBERIAN CONFERENCE ON CONTROL AND COMMUNICATIONS (SIBCON), 2016,