Statistical analysis of spurious dot formation in silicon metal-oxide-semiconductor single electron transistors

被引：0

作者：

Chen, Kuan-Chu ^{[1
]}

Godfrin, Clement ^{[1
]}

Simion, George ^{[1
]}

Fattal, Imri ^{[1
,2
]}

Jussot, Julien ^{[1
]}

Kubicek, Stefan ^{[1
]}

Beyne, Sofie ^{[1
]}

Raes, Bart ^{[1
]}

Loenders, Arne ^{[1
,2
]}

Kao, Kuo-Hsing ^{[3
]}

Wan, Danny ^{[1
]}

De Greve, Kristiaan ^{[1
,2
]}

机构：

[1] IMEC, Leuven,3001, Belgium

[2] Department of Electrical Engineering, KU Leuven, Leuven,3001, Belgium

[3] Department of Electrical Engineering, National Cheng Kung University, Tainan,701401, Taiwan

来源：

Physical Review B | 2025年 / 111卷 / 12期

基金：

欧盟地平线“2020”;

关键词：

Gallium phosphide - Gates (transistor) - Indium phosphide - MOS devices - Nanocrystals - Oxide semiconductors - Polycrystalline materials - Semiconducting silicon compounds - Semiconductor quantum dots - Silicon wafers;

D O I：

10.1103/PhysRevB.111.125301

中图分类号：

学科分类号：

摘要：

The spatial distribution of spurious dots in SiMOS single-electron transistors (SETs), fabricated on an industrial 300 mm process line, has been statistically analyzed. To have a deeper understanding of the origin of these spurious dots, we analyzed SETs with three different oxide thicknesses: 8, 12, and 20 nm. By combining spurious dot triangulation cryo measurement with simulations of strain, gate bias, and location of the electron wave function, we demonstrate that most spurious dots are formed through the combined effects of strain and gate bias, leading to variations in the conduction band energy. Despite the similar thermal expansion coefficients of polycrystalline silicon gates and single-crystalline silicon substrates, strain remains a crucial factor in spurious dot formation. This learning can be used to optimize the device design and the oxide thickness, to reduce the density of spurious dot while keeping quantum dot tunability. © 2025 American Physical Society.

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