Suppression of effects of parasitic metal-oxide-semiconductor field-effect transistors on Si single-electron transistors

Si single-electron transistors (SETs), which are fabricated in ultrathin Si of a silicon-on-insulator substrate by pattern-dependent oxidation, are accompanied by parasitic metal-oxide-semiconductor field-effect transistors (MOSFETs) on both sides of the SET. While the Si island of a SET is formed by design in a one-dimensional Si wire, the parasitic MOSFETs are inevitably formed in two-dimensional Si pad layers, between which the Si wire runs, because the poly-Si gate covers the Si pad layers as well as the Si island. Electrical characteristics of the device are strongly affected by these parasitic MOSFETs because of their relatively high resistance or the Coulomb blockade effect due to multiple islands unintentionally formed in the pad Si layers. We found that backgate voltage is useful for reducing or analyzing such parasitic effects. We propose a new fabrication technique; the use of a SiN mask for oxidation avoids unnecessary thinning of pad Si layers and parasitic effects can be suppressed.