An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology

This study delves into the computational aspects of ternary logic and the use of carbon nanotube fi eld- effect transistors ( CNTFETs ) to develop an energy-efficient and robust ternary multiplier ( TMUL ) . Leveraging the exceptional qualities of CNTFETs, such as balanced electron and hole mobility and easy modulation of threshold voltage, the research aims to achieve the desired designs. An innovative design method is employed, recommending a reduced count of logic gates for achieving necessary logic levels. These gates are then utilized to manage the activation and deactivation of the primary transistors within the TMUL cell to convey the intended logics to the outputs. Moreover, the suggested design is focused on a single-V-DD, enhancing compatibility with the goals of a multi-valued logic platform. The proposed circuit is validated using Synopsis HSPICE simulator and Stanford's standard 32-nm CNTFET model fi le. Comparative analysis with existing TMUL designs demonstrates a 25.43% decrease in average power consumption, a 42.24% reduction in power-delay product ( PDP ) , and a 24.69% decrease in energy-delay product ( EDP ) . The design undergoes thorough simulations under various conditions including load variations and process, voltage, and temperature ( PVT ) fl uctuations to confirm its reliability and robustness.