A 2-GS/s 6-bit Single-channel Speculative Loop-unrolled SAR ADC with Low-overhead Comparator Offset Calibration in 28-nm CMOS

This paper presents a 2-GS/s 6-bit single- channel speculative loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with comparator offset calibration. The proposed loop-unrolled SAR ADC speeds up its conversion speed by selecting one of the predetermined capacitive digital-to-analog converters (CDACs) speculatively. A foreground comparator offset calibration for the speculative loop-unrolled SAR ADC is introduced to improve the ADC performance by reducing the input parasitic capacitance and minimizing the logic fan-out in comparator internal clock path. The CDAC switching method that minimizes the variation of the output common-mode (CM) voltage is applied to be compatible with the proposed foreground comparator offset calibration. In addition, the modified double- tail comparator structure is adopted for reducing the kickback noise without the speed overhead. The proposed SAR ADC achieves a 2-GS/s sampling rate with only a single-channel without a time-interleaving technique. The ADC is fabricated in 28-nm CMOS and has a 33.1-dB SNDR at a low input frequency and a 29.9-dB SNDR at the Nyquist frequency with a 6.2mW power consumption from 1.2-V supply voltage.