A Novel Five-Level Knight Multilevel Inverter With Phase Disposition Modulation Technique

被引:0
|
作者
Sambhavi, Y. Vijaya [1 ]
Vijayapriya, R. [1 ]
机构
[1] Vellore Inst Technol, Sch Elect Engn, Vellore 632014, Tamil Nadu, India
来源
IEEE ACCESS | 2024年 / 12卷
关键词
Topology; Pulse width modulation; Voltage; Capacitors; Switches; Clamps; Voltage control; Multilevel inverters; Harmonic analysis; Transformers; Control techniques; electric vehicles; multilevel inverter; neutral-point clamped inverter; phase disposition; voltage source inverter; PWM; TOPOLOGIES; CONVERTERS; SCHEMES; SYSTEM;
D O I
10.1109/ACCESS.2024.3501333
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A novel five-level (5L) Knight MLI for power electronics applications is proposed in this paper. The proposed inverter is constructed by modifying the conventional 5L neutral point clamped multilevel inverter (NPC MLI). The NPC MLI architecture involves a large number of components for higher level and higher switching frequency operation. In this work paper, the proposed 3 Phi 5L-Knight MLI is made up by evading the usage of clamping diodes, series switches, and quadratic switches. Additionally, the phase disposition pulse width modulation (PD-PWM) control technique is also employed for the proposed 3 Phi 5 L-Knight MLI. Compared to other traditional 5L topologies, this proposed Knight MLI has fewer components and a high-quality output voltage. It can operate at several different ranges of voltage ratings without requiring power semiconductors to be connected in series. In comparison to the NPC MLI, the proposed MLI reduces the switching stress as two switches are operated per inverter leg instead of four switches. Another feature is that there is a considerable reduction in power losses as the current flows only through fewer elements. The topology attained an efficiency of approximately 92.39% under dynamic loading. Around 75% of the switches encountered one-quarter of the peak output voltage V-dc, 20% of the switches experienced half of the peak output voltage V-dc, and the remaining switches faced the peak output voltage V-dc as voltage stress. The proposed 5L MLI topology is explored thoroughly using the MATLAB simulation model. The evaluation of results is also demonstrated concerning the proposed PD-PWM technique by comparing its performance with the conventional sinusoidal PWM method. The real-time hardware-in-loop (HIL) simulator is also used to validate the simulation outcomes of the suggested model.
引用
收藏
页码:170499 / 170513
页数:15
相关论文
共 50 条
  • [31] A new type of single-phase five-level inverter
    Xu, Zhi
    Li, Shengnan
    Qin, Risheng
    Zhao, Yanhang
    2017 3RD INTERNATIONAL CONFERENCE ON ENERGY, ENVIRONMENT AND MATERIALS SCIENCE (EEMS 2017), 2017, 94
  • [32] Modeling of Five-Level Symmetric Flying Capacitor Multilevel Inverter for STATCOM Application
    Humayun, Muhammad
    Khan, Muhammad Mansoor
    Zhang Weidong
    Jiang Huawei
    Ullah, Mati
    2017 13TH INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES (ICET 2017), 2017,
  • [33] A Novel Modulation Technique and a New Balancing Control Strategy for a Single-Phase Five-Level ANPC Converter
    Teymour, Hamid R.
    Sutanto, Danny
    Muttaqi, Kashem M.
    Ciufo, P.
    IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2015, 51 (02) : 1215 - 1227
  • [34] Capacitor voltage balancing using redundant states for five-level multilevel inverter
    Hotait, Hadi A.
    Massoud, Ahmed M.
    Finney, Steve J.
    Williams, Barry W.
    2007 INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND DRIVE SYSTEMS, VOLS 1-4, 2007, : 1255 - 1261
  • [35] Backstepping controller of five-level three-phase inverter
    Majdoul, R.
    Abouloifa, A.
    Abdelmounim, E.
    Aboulfatah, M.
    Touati, A.
    Moutabir, A.
    CSNDD 2014 - INTERNATIONAL CONFERENCE ON STRUCTURAL NONLINEAR DYNAMICS AND DIAGNOSIS, 2014, 16
  • [36] A Single-Phase Five-Level Transformerless Photovoltaic Inverter
    Zhu, Xiaonan
    Chcn, Xinyue
    Sun, Renjie
    Li, Zhenzhen
    Yue, Xiumei
    Wang, Hongliang
    2020 THIRTY-FIFTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2020), 2020, : 3215 - 3220
  • [37] Experimental verification for improved phase-disposition PWM of three-phase five-level diode-clamped inverter
    Suleiman, Mohammad
    Elnady, A.
    Osman, Ahmed
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2021, 49 (06) : 1828 - 1848
  • [38] A Novel Three-Phase Switched-Capacitor Five-Level Multilevel Inverter with Reduced Components and Self-Balancing Ability
    Jena, Kasinath
    Kumar, Dhananjay
    Janardhan, Kavali
    Kumar, B. Hemanth
    Singh, Arvind R.
    Nikolovski, Srete
    Bajaj, Mohit
    APPLIED SCIENCES-BASEL, 2023, 13 (03):
  • [39] THD Minimization in a Five-Phase Five-Level VSI Using a Novel SVPWM Technique
    Booin, Mohammad Bayati
    Cheraghi, Mohsen
    2019 10TH INTERNATIONAL POWER ELECTRONICS, DRIVE SYSTEMS AND TECHNOLOGIES CONFERENCE (PEDSTC), 2019, : 285 - 290
  • [40] Fault Recognition and Reconfiguration for Three-Phase Five-level Cascaded H-bridge Multilevel Inverter
    Prasad T.
    Pattnaik S.
    Radioelectronics and Communications Systems, 2022, 65 (06) : 317 - 329