A Novel Five-Level Knight Multilevel Inverter With Phase Disposition Modulation Technique

被引:0
|
作者
Sambhavi, Y. Vijaya [1 ]
Vijayapriya, R. [1 ]
机构
[1] Vellore Inst Technol, Sch Elect Engn, Vellore 632014, Tamil Nadu, India
来源
IEEE ACCESS | 2024年 / 12卷
关键词
Topology; Pulse width modulation; Voltage; Capacitors; Switches; Clamps; Voltage control; Multilevel inverters; Harmonic analysis; Transformers; Control techniques; electric vehicles; multilevel inverter; neutral-point clamped inverter; phase disposition; voltage source inverter; PWM; TOPOLOGIES; CONVERTERS; SCHEMES; SYSTEM;
D O I
10.1109/ACCESS.2024.3501333
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A novel five-level (5L) Knight MLI for power electronics applications is proposed in this paper. The proposed inverter is constructed by modifying the conventional 5L neutral point clamped multilevel inverter (NPC MLI). The NPC MLI architecture involves a large number of components for higher level and higher switching frequency operation. In this work paper, the proposed 3 Phi 5L-Knight MLI is made up by evading the usage of clamping diodes, series switches, and quadratic switches. Additionally, the phase disposition pulse width modulation (PD-PWM) control technique is also employed for the proposed 3 Phi 5 L-Knight MLI. Compared to other traditional 5L topologies, this proposed Knight MLI has fewer components and a high-quality output voltage. It can operate at several different ranges of voltage ratings without requiring power semiconductors to be connected in series. In comparison to the NPC MLI, the proposed MLI reduces the switching stress as two switches are operated per inverter leg instead of four switches. Another feature is that there is a considerable reduction in power losses as the current flows only through fewer elements. The topology attained an efficiency of approximately 92.39% under dynamic loading. Around 75% of the switches encountered one-quarter of the peak output voltage V-dc, 20% of the switches experienced half of the peak output voltage V-dc, and the remaining switches faced the peak output voltage V-dc as voltage stress. The proposed 5L MLI topology is explored thoroughly using the MATLAB simulation model. The evaluation of results is also demonstrated concerning the proposed PD-PWM technique by comparing its performance with the conventional sinusoidal PWM method. The real-time hardware-in-loop (HIL) simulator is also used to validate the simulation outcomes of the suggested model.
引用
收藏
页码:170499 / 170513
页数:15
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