RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost

被引:0
|
作者
Gajjar, Archit [1 ,2 ]
Kashyap, Priyank [2 ,3 ]
Aysu, Aydin [2 ]
Franzon, Paul [2 ]
Choi, Yongjin [3 ]
Cheng, Chris [4 ]
Pedretti, Giacomo [5 ]
Ignowski, Jim [1 ]
机构
[1] Hewlett Packard Labs, Artificial Intelligence Res Lab AIRL, Ft Collins, CO 95035 USA
[2] North Carolina State Univ, Raleigh, NC 27695 USA
[3] Hewlett Packard Enterprise, Colorado Springs, CO USA
[4] Hewlett Packard Enterprise, San Jose, CA USA
[5] Hewlett Packard Labs, Artificial Intelligence Res Lab AIRL, Milpitas, CA USA
基金
美国国家科学基金会;
关键词
FPGAs; XGBoost; Binary Classification; High-Level Synthesis; Ransomware; Hardware Performance Counters; Accelerators; Machine Learning; DECISION TREE; CLASSIFICATION;
D O I
10.1145/3688396
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Over the last decade, there has been a rise in cyberattacks, particularly ransomware, causing significant disruption and financial repercussions across public and private sectors. Tremendous efforts have been spent on developing techniques to detect ransomware to, ideally, protect data or have as minimum data loss as possible. Ransomware attacks are becoming more frequent and sophisticated as there is a constant tussle between attackers and cybersecurity defenders. Machine Learning (ML) approaches have proven more effective in detecting ransomware than classical signature-based detection. In particular, tree-based algorithms such as Decision Trees (DT), Random Forest (RF), and eXtreme Gradient Boosting (XGBoost) spike up interest among cybersecurity researchers. However, due to the nature of the problem, traditional CPUs and GPUs fail to keep up with the desired performance, especially for large data workloads. Thus, the problem demands a customized solution to detect the ransomware. Here, we propose an FPGA accelerated tree-based ML model for multi-dataset ransomware detection. We show the capability of the proposed prototype to address the problem from more than one set of features, reducing false positive and negative rates to have robust predictions by looking at Hardware Performance Counters (HPCs), Operating System (OS) calls, and network traffic information simultaneously. With 1,000 samples per batch, the FPGA prototype has 65.8x and 4.1x lower latency over the CPU and GPU, respectively. Moreover, the FPGA design is up to 11.3x cost-effective and 643x energy-efficient compared to the CPU and 3x cost-effective and 16.8x energy-efficient over the GPU.
引用
收藏
页数:33
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