HARDWARE VERIFICATION AT FUNCTIONAL DESIGN STAGE.

被引:0
|
作者
Maruyama, Fumhiro
机构
关键词
D O I
暂无
中图分类号
学科分类号
摘要
The paper considers the reliability in logic design. A new method of verification is described that detects the inconsistencies in the hardware functional descriptions and verifies that the hardware meets the given specifications. This method is aimed basically at verifying the logic design of large-scale computers and provides an effective verification algorithm for checking the interfaces between units, in which problems of erroneous design are more frequent.
引用
收藏
页码:152 / 161
相关论文
共 50 条
  • [31] Determination of the Quantities of Steel Needed for Reinforced Concrete at the Design Stage.
    Thonier, Henry
    1600, (38):
  • [32] The Fuzz Odyssey: A Survey on Hardware Fuzzing Frameworks for Hardware Design Verification
    Saravanan, Raghul
    Dinakarrao, Sai Manoj Pudukotai
    PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, 2024, : 192 - 197
  • [33] FATIGUE LIFE PREDICTION FOR GAUSSIAN RANDOM LOADS AT THE DESIGN STAGE.
    Tunna, J.M.
    Fatigue and Fracture of Engineering Materials and Structures, 1986, 9 (03): : 169 - 184
  • [34] Comparable Estimation of the Efficiency of Telecommunication Systems during the Design Stage.
    Yurlov, F.F.
    Izvestiya Vysshikh Uchebnykh Zavedenij. Radioelektronika, 1975, 18 (01): : 119 - 121
  • [35] SYSTEM FOR THE PREDICTION OF HULL AND SUPERSTRUCTURE VIBRATION AT AN EARLY DESIGN STAGE.
    Ohta, Tohru
    Satoh, Hirokazu
    Sugiyama, Kyota
    Kondo, Kiyoshi
    Sugita, Shinichi
    Nippon Kokan technical report overseas, 1983, (39): : 98 - 107
  • [36] IMPROVEMENT IN THE METHOD OF CHOOSING VERSIONS OF POWER EQUIPMENT AT THE DESIGN STAGE.
    Smolkin, Yu.V.
    Suvorov, P.P.
    Soviet energy technology, 1986, (12): : 8 - 12
  • [37] THEORETICAL RESEARCH OF AN OPTIMUM DESIGN METHOD FOR THE AXIAL TURBINE STAGE.
    Zou, Zixang
    Jixie goneheng Xuebao, 1984, 20 (01): : 83 - 95
  • [38] Functional Verification of Hardware Dividers using Algebraic Model
    Yasin, Atif
    Su, Tiankai
    Pillement, Sebastien
    Ciesielski, Maciej
    2019 IFIP/IEEE 27TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2019, : 257 - 262
  • [39] Hardware emulation for functional verification of K5
    Ganapathy, G
    Narayan, R
    Jorden, G
    Fernandez, D
    Wang, M
    Nishimura, J
    33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 315 - 318
  • [40] Robust Partitioning for Hardware-Accelerated Functional Verification
    Moffitt, Michael D.
    Sustik, Matyas A.
    Villarrubia, Paul G.
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 854 - 859