共 50 条
- [4] A fractional delay-locked loop for on chip clock generation applications ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 1300 - 1303
- [8] Design techniques of delay-locked loop for jitter minimization in DRAM applications IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (04): : 753 - 759
- [10] A Multiphase Delay-Locked Loop with Interleaving Calibration 2014 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE, ELECTRONICS AND ELECTRICAL ENGINEERING (ISEEE), VOLS 1-3, 2014, : 236 - +