Test Generation for Stuck-on Faults in Pass-Transistor Logic SPL and Implementation of DFT Circuits

被引：0

作者：

Shinogi, Tsuyoshi

Hayashi, Terumine

Taki, Kazuo

机构：

[1] Graduate School of Engineering, Mie University, Tsu, 514-8507, Japan

[2] Faculty of Engineering, Kobe University, Kobe, 657-8501, Japan

来源：

Systems and Computers in Japan | 1999年 / 30卷 / 07期

关键词：

D O I：

10.1002/(SICI)1520-684X(19990630)30:73.0.CO;2-9

中图分类号：

学科分类号：

摘要：

引用

页码：55 / 67

共 43 条

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Shinogi, T
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SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 16 - 21
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Rashid, ABMH
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[3] Constructing testable differential pass-transistor logic circuits
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[9] Design of dynamic pass-transistor logic circuits using 123 decision diagrams
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Jullien, GA
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1998, 45 (11) : 1172 - 1181
[10] Testability of 123DD based differential pass-transistor logic circuits
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IMTC/99: PROCEEDINGS OF THE 16TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE, VOLS. 1-3, 1999, : 1782 - 1787

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