Test generation for stuck-on faults in BDD-based pass-transistor logic SPL

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作者
Shinogi, T
Hayashi, T
Taki, K
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中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem, we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.
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页码:16 / 21
页数:6
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