Design of ECL 1-Mb BiCMOS DRAM

This paper describes an experimental 1,3-μm, 1-Mb BiCMOS DRAM, the first DRAM to use an ECL interface. The results are as follows: (1) quantitative analysis shows that direct sensing of a small read-signal voltage on the data lines before amplification by the CMOS rewrite amplifier gives an access time 8 ns (up to about 30 percent) faster than conventional common input/output (I/O) sensing; (2) the bipolar cascode amplifier is characterized by the pulsed emitter-bias current. Computer simulation and experiments show that its delay time is not sensitive to changes in Vcc at the rate of about 50 mV/ns; (3) a new bipolar ECL I/O circuit with a power-switching function is shown to reduce the standby current of a 1-Mb ECL chip to about one-fifth that of an ECL chip without a power-switching function; and (4) the experimental chip has an access time of 24 ns, power dissipation of 730 mW, and a chip area of 62.2 mm2 under typical conditions of VEE = -5.2 V, Ta = 25°C, output capacitance CL = 10 pF and a cycle time of 70 ns, and nMOS/pMOS transistors with gate lengths of 1.4/1.7 μm.