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- [3] 45nm/32nm CMOS - Challenge and perspective - ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 32 - +
- [5] Cell projection use in mask-less lithography for 45nm & 32nm logic nodes ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES, 2009, 7271
- [6] Using CMP Model for 45nm/32nm BEOL Process and Design Evaluations CHEMICAL MECHANICAL POLISHING 11, 2010, 33 (10): : 3 - 7
- [7] Optical issues of thin organic pellicles in 45nm and 32nm immersion lithography PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2, 2006, 6349
- [8] Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm) ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, : 25 - 30
- [9] 45nm and 32nm half-pitch patterning with 193nm dry lithography and double patterning OPTICAL MICROLITHOGRAPHY XXI, PTS 1-3, 2008, 6924
- [10] RET application in 45nm node and 32nm node contact hole dry ArF lithography process development OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520