Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects

被引:0
|
作者
Taylor, Gregory F. [1 ]
Arabi, Tawfik [1 ]
Greub, Hans [1 ]
Muyshondt, Richard [1 ]
Manthe, Alicia [1 ]
Aminzadeh, Payman [1 ]
机构
[1] Intel Corp, Hillsboro, United States
关键词
CMOS integrated circuits - Current density - Electric potential - Electromigration - Hot carriers - Integrated circuit layout - Oxides - Reliability;
D O I
暂无
中图分类号
学科分类号
摘要
The performance of CMOS integrated circuits has always been, and continues to be, limited by reliability considerations. Performance, reliability and cost are traded off through voltage and temperature specifications. The temperature acceleration of breakdown in oxides is increasing with decreasing thickness, current densities are increasing further stressing electromigration, inductive noise effects are becoming more significant while soft error susceptibility is increasing. In addition to all of these deleterious effects, oxide wear out has become a major factor in determining lifetime of very thin oxides. The design and validations issues associated with oxide wear out failure mechanisms are discussed.
引用
收藏
页码:49 / 52
相关论文
共 50 条
  • [31] On skin effect in on-chip interconnects
    Andersson, DA
    Svensson, L
    Larsson-Edefors, P
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2004, 3254 : 463 - 470
  • [32] Exploiting Emergence in On-Chip Interconnects
    Hollis, Simon J.
    Jackson, Chris
    Bogdan, Paul
    Marculescu, Radu
    IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (03) : 570 - 582
  • [33] Unified model for on-chip interconnects
    Yu, S
    Sim, SP
    Krishnan, S
    Petranovic, DM
    Lee, K
    Yang, CY
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1026 - 1031
  • [34] Inductance modeling for on-chip interconnects
    Tu, SW
    Shen, WZ
    Chang, YW
    Chen, TC
    Jou, JY
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2003, 35 (01) : 65 - 78
  • [35] Efficient macromodeling for on-chip interconnects
    Xu, QW
    Mazumder, P
    ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 561 - 566
  • [36] Inductance modeling for on-chip interconnects
    Tu, SW
    Shen, WZ
    Chang, YW
    Chen, TC
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 787 - 790
  • [37] Two high-performance and low-power serial communication interfaces for on-chip interconnects
    Saneei, Mohsen
    Afzali-Kusha, Ali
    Pedram, Massoud
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2009, 34 (1-2): : 49 - 56
  • [38] A Survey of On-Chip Optical Interconnects
    Bashir, Janibul
    Peter, Eldhose
    Sarangi, Smruti R.
    ACM COMPUTING SURVEYS, 2019, 51 (06)
  • [39] Copper metallization for on-chip interconnects
    Gelatos, AV
    Nguyen, BY
    Perry, K
    Marsh, R
    Peschke, J
    Filipiak, S
    Travis, E
    Thompson, M
    Saaranen, T
    Tobin, PJ
    Mogab, CJ
    MICROELECTRONIC DEVICE AND MULTILEVEL INTERCONNECTION TECHNOLOGY II, 1996, 2875 : 346 - 357
  • [40] Efficient on-chip global interconnects
    Ho, R
    Mai, K
    Horowitz, M
    2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, : 271 - 274