Reducing test application time for full scan embedded cores

被引：0

作者：

Hamzaoglu, Ilker ^{[1
]}

Patel, Janak H. ^{[1
]}

机构：

[1] Univ of Illinois, Urbana, United States

来源：

Proceedings - Annual International Conference on Fault-Tolerant Computing | 1999年

关键词：

Combinatorial circuits - Computational complexity - Embedded systems - Fast Fourier transforms - Integrated circuit testing - Microprocessor chips - Sequential circuits - Vectors;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PSFS technique significantly reduces both the test application time and the amount of test data for full scan embedded cores.

引用

页码：260 / 267

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