High pin-count PBGA assembly

被引：0
|
作者：
Fauser, Suzanne [1 ]
Ramirez, Cynthia [1 ]
Hollinger, Larry [1 ]
机构：
[1] Wavetek, Indianapolis, United States
来源：
Circuits Assembly | 1995年 / 6卷 / 02期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] General Purpose Cross-Referencing Microfluidic Biochip with Reduced Pin-Count
    Yeung, Jackson H. C.
    Young, Evangeline F. Y.
    2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 238 - 243
  • [22] ESD protection design challenges for a high pin-count alpha microprocessor in a 0.13 μm CMOS SOI technology
    Juliano, PA
    Anderson, WR
    JOURNAL OF ELECTROSTATICS, 2004, 62 (2-3) : 113 - 131
  • [23] Microwave Induced Plasma Decapsulation of Stressed and Delaminated High Pin-count Copper Wire Bonded IC Packages
    Tang, J.
    Chen, C. H.
    Liang, S. K.
    Reinders, E. G. J.
    Revenberg, C. Th A.
    Schelen, J. B. J.
    Beenakker, C. I. M.
    2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 1717 - 1723
  • [24] Automated Design of Digital Microfluidic Lab-on-Chip under Pin-Count Constraints
    Xu, Tao
    Chakrabarty, Krishnendu
    ISPD'08: PROCEEDINGS OF THE 2008 ACM INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, 2008, : 190 - 198
  • [25] An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing
    Hsieh, Tong-Yu
    Wang, Tai-Ping
    Yang, Shuo
    Hsu, Chin-An
    Lin, Yi-Lung
    IEICE TRANSACTIONS ON ELECTRONICS, 2016, E99C (03): : 404 - 414
  • [26] Test resource partitioning and reduced pin-count testing based on test data compressioni
    Chandra, A
    Chakrabarty, K
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 598 - 603
  • [27] LOW-COST PROGRAMMABLE SOURCES EXPAND ATE PIN-COUNT CAPABILITIES.
    Gantt, Philip R.
    Anding, Martin E.
    EDN, 1984, 29 (03): : 220 - 224
  • [28] PCB Power Integrity Flow - Efficiently Designing-in Large Pin-count, Smaller Pitch Devices
    Socha, Joe
    Chitwood, Sam
    Brim, Bradley
    2017 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & SIGNAL/POWER INTEGRITY (EMCSI), 2017,
  • [29] Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs
    Richter, Michael
    Chakrabarty, Krishnendu
    IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (03) : 691 - 702
  • [30] Very high pin count flip chip assembly using conductive polymer adhesives
    Clayton, JE
    2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 2003, 5288 : 275 - 281
12345