MULTI-PROCESSOR ARCHITECTURE FOR SIMULATION.

被引:0
|
作者
McQuade, Michael R.
Alford, Cecil O.
机构
关键词
Compendex;
D O I
暂无
中图分类号
学科分类号
摘要
COMPUTER ARCHITECTURE
引用
收藏
页码:42 / 46
相关论文
共 50 条
  • [21] Server-based data push architecture for multi-processor environments
    Sun, Xian-He
    Byna, Surendra
    Chen, Yong
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2007, 22 (05) : 641 - 652
  • [22] Performance simulation of multi-processor systems based on load reallocation
    Jaakola, Marko
    VTT Publications, 2009, (717): : 1 - 65
  • [23] Server-Based Data Push Architecture for Multi-Processor Environments
    Xian-He Sun
    Surendra Byna
    Yong Chen
    Journal of Computer Science and Technology, 2007, 22 : 641 - 652
  • [24] An Accelerated Architecture Based on GPU and Multi-Processor Design for Fingerprint Recognition
    Ben Ayed, Mossaad
    Elkosantini, Sabeur
    INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2016, 7 (03) : 337 - 348
  • [25] A Variation Tolerant Architecture for Ultra Low Power Multi-processor Cluster
    Bortolotti, Daniele
    Rossi, Davide
    Bartolini, Andrea
    Benini, Luca
    2013 23RD INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2013, : 32 - 38
  • [26] Server-Based Data Push Architecture for Multi-Processor Environments
    孙贤和
    Surendra Byna
    陈勇
    JournalofComputerScience&Technology, 2007, (05) : 641 - 652
  • [27] A multi-processor control system architecture for a cascaded StatCom with energy storage
    Qian, C
    Crow, ML
    Atcitty, S
    APEC 2004: NINETEENTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1-3, 2004, : 1757 - 1763
  • [28] A consideration of processor utilization on multi-processor system
    Kashiwagi, Koichi
    Higami, Yoshinobu
    Kobayashi, Shin-Ya
    ADVANCES IN INFORMATION PROCESSING AND PROTECTION, 2007, : 383 - 390
  • [29] Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding
    Jan, Yahya
    Jozwiak, Lech
    MICROPROCESSORS AND MICROSYSTEMS, 2014, 38 (02) : 152 - 169
  • [30] Shared multi-processor scheduling
    Dereniowski, Dariusz
    Kubiak, Wieslaw
    EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 2017, 261 (02) : 503 - 514