CHANNEL ION IMPLANTATION FOR SMALL-GEOMETRY HIGH-PERFORMANCE CMOS-SOS CIRCUITS.

被引：0

作者：

Lewis, Alan G. ^{[1
]}

Brassington, Michael P. ^{[1
]}

Partridge, Susan L. ^{[1
]}

机构：

[1] GEC Research Ltd, Wembley, Engl, GEC Research Ltd, Wembley, Engl

来源：

IEEE Transactions on Electron Devices | 1986年 / ED-33卷 / 03期

关键词：

INTEGRATED CIRCUITS; VLSI - Fabrication - SEMICONDUCTING SILICON - Ion Implantation - SEMICONDUCTOR DEVICE MANUFACTURE - Silicon on Sapphire Technology;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Tha authors describe an experimental study of channel ion implantation for optimization of small-geometry (1-1. 5 mu m) n- and p-channel silicon-on-sapphire (SOS) MOSFETs for high-performance CMOS applications. The influence of a wide range of channel implantation conditions on device characteristics are reported, and optimum channel doping profiles identified. Adequate performance of NMOS devices is achieved by the use of double boron channel implants, but excellent PMOS devices are obtained by the use of very lightly doped near-intrinsic device islands.

引用

页码：335 / 344

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