IMPLANTATION-DOMINATED JUNCTION DEPTHS OF LOW-TEMPERATURE AND ELECTRON-BEAM-ANNEALED AS SOURCE-DRAIN REGIONS.

被引：0
|
作者：
Amaratunga, G.A.J. [1 ]
Knee, N.D. [1 ]
Hart, M.J. [1 ]
Evans, A.G.R. [1 ]
机构：
[1] Univ of Southampton, Engl, Univ of Southampton, Engl
来源：
IEEE Transactions on Electron Devices | 1987年 / ED-34卷 / 02期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
SEMICONDUCTOR DEVICES, MOS
引用
收藏
页码：445 / 448
相关论文
共 11 条
  • [1] IMPLANTATION-DOMINATED JUNCTION DEPTHS OF LOW-TEMPERATURE AND ELECTRON-BEAM-ANNEALED AS SOURCE DRAIN REGIONS
    AMARATUNGA, GAJ
    KNEE, ND
    HART, MJ
    EVANS, AGR
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (02) : 445 - 448
  • [2] CMOS Inverter Based on Schottky Source-Drain MOS Technology With Low-Temperature Dopant Segregation
    Larrieu, Guilhem
    Dubois, Emmanuel
    IEEE ELECTRON DEVICE LETTERS, 2011, 32 (06) : 728 - 730
  • [3] Low-Vt TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions
    Lin, S. H.
    Liu, S. L.
    Yeh, F. S.
    Chin, Albert
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (01) : 75 - 77
  • [4] Low-temperature formation of source-drain contacts in self-aligned amorphous oxide thin-film transistors
    Naga, Manoj
    Muller, Robert
    Steudel, Soeren
    Smout, Steve
    Bhoolokama, Ajay
    Myny, Kris
    Schols, Sarah
    Genoe, Jan
    Cobb, Brian
    Kumar, Abhishek
    Gelinck, Gerwin
    Fukui, Yusuke
    Groesenekena, Guido
    Heremans, Paul
    JOURNAL OF INFORMATION DISPLAY, 2015, 16 (02) : 111 - 117
  • [5] Low-Temperature Processed Polycrystalline Silicon Thin-Film Transistor with Aluminum-Replaced Source and Drain Regions
    Zhang, Dongli
    Kwok, Hoi-Sing
    Wong, Man
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 974 - 977
  • [6] Low leakage current and low resistivity p+n diodes on Si(110) fabricated by Ga+ and B+ dual ion implantation for low temperature source-drain activation
    Imai, Hiroshi
    Teramoto, Akinobu
    Sugawa, Shigetoshi
    Ohmi, Tadahiro
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2007, 46 (4 B): : 1848 - 1852
  • [7] Low leakage current and low resistivity p+n diodes on Si(110) fabricated by Ga+ and B+ dual ion implantation for low temperature source-drain activation
    Imai, Hiroshi
    Teramoto, Akinobu
    Sugawa, Shigetoshi
    Ohmi, Tadahiro
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (4B): : 1848 - 1852
  • [8] New structure of polycrystalline silicon thin-film transistor with germanium layer in source/drain regions for low-temperature device fabrication
    Mitsui, Minoru
    Arimoto, Keisuke
    Yamanaka, Junji
    Nakagawa, Kiyokazu
    Sawano, Kentarou
    Shiraki, Yasuhiro
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (03) : 1547 - 1549
  • [9] Hot-carrier degradation and electric field and electron concentration near drain junction in low-temperature n-channel single drain and lightly doped drain polycrystalline silicon thin film transistors
    Usami, Gen
    Nogami, Yukisato
    Yajima, Toshihisa
    Yamagata, Masahiro
    Satoh, Toshifumi
    Tango, Hiroyuki
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (3B): : 1322 - 1327
  • [10] Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions
    Wang, Yu-Xuan
    Tai, Mao-Chou
    Chang, Ting-Chang
    Huang, Shin-Ping
    Zheng, Yu-Zhe
    Wu, Chia-Chuan
    Shih, Yu-Shan
    Chen, Yu-An
    Sun, Pei-Jun
    Lu, I-Nien
    Huang, Hui-Chun
    Sze, Simon M.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (12) : 5552 - 5556
12