Low leakage current and low resistivity p+n diodes on Si(110) fabricated by Ga+ and B+ dual ion implantation for low temperature source-drain activation

被引：0
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作者：
Imai, Hiroshi [1 ]
Teramoto, Akinobu [2 ]
Sugawa, Shigetoshi [1 ]
Ohmi, Tadahiro [2 ]
机构：
[1] Graduate School of Engineering, Tohoku University, Sendai 980-8579, Japan
[2] New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan
来源：
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2007年 / 46卷 / 4 B期
关键词：
Low leakage current and low resistivity p+n diodes on Si(110) were formed by low temperature annealing at around 550°C. Ga+ and B + dual (Ga+/B+) ion implantation on Si(110) followed by low temperature annealing was studied. We demonstrated that Ga +/B+ ion implantation can make the high carrier density p+ layer on Si(110) at low temperature annealing. The p+n diodes of Ga+/B+ implanted on Si(110) followed by low temperature annealing show the ideal leakage current characteristics at room temperature. This result can apply to form the source-drain region of complementary metal-oxide-semiconductor (CMOS) devices at low temperature annealing; especially the devices fabricated on Si(110). © 2007 The Japan Society of Applied Physics;
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页码：1848 / 1852
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