共 50 条
- [21] Resynthesis of combinational circuits for path count reduction and for path delay fault testability EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS, 1996, : 486 - 490
- [22] Resynthesis of combinational circuits for path count reduction and for path delay fault testability JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1997, 11 (01): : 43 - 54
- [23] Minimal logic re-synthesis for engineering change ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 1596 - 1599
- [25] A minimum cut based re-synthesis approach 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 202 - 207
- [26] Re-synthesis in technology mapping for heterogeneous FPGAs INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 202 - 204
- [28] MILLER RE - SWITCHING THEORY . COMBINATIONAL CIRCUITS . SEQUENTIAL CIRCUITS AND MACHINES COMPUTER JOURNAL, 1966, 9 (02): : 143 - &
- [29] Synthesis and Optimization of Combinational Interface Circuits Journal of VLSI signal processing systems for signal, image and video technology, 2002, 31 : 243 - 261
- [30] Synthesis and Verification of Cyclic Combinational Circuits 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 257 - 262