Scalable, real-time, image processing pipeline

To speed up image processing in the field of robot vision and industrial inspection, a pipeline element that can perform fast cellular logic operations was made. This cellular logic processing element (CLPE) can process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI device. It includes a writable logic array for storing sets of 3×3 structuring elements that define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed gray-value processing and cellular logic processing.