LOGIC NETWORK SYNTHESIS USING DIGITAL-SUMMATION THRESHOLD-LOGIC GATES.

被引：0

作者：

Hurst, S.L.

机构：

来源：

Microelectronics Journal | 1975年 / 6卷 / 04期

关键词：

LOGIC DEVICES - Threshold Elements;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The recently-developed Digital-Summation Threshold-Logic (DSTL) gate s introduced, and its advantages and disadvantages re discussed in comparison with previous analog-type threshold-logic gates. Some typical applications are shown indicating package and pin savings in random-logic networks. Consideration of optimum universal package specifications for random-logic work is mentioned.

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页码：42 / 48

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[1] NOTE ON DIGITAL-SUMMATION THRESHOLD-LOGIC GATES
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