NOTE ON DIGITAL-SUMMATION THRESHOLD-LOGIC GATES

被引：0

|

作者：

PRATAPAR.VC ^{[1
]}

NEELAKANTASWAMY, PS ^{[1
]}

机构：

[1] INDIAN INST TECHNOL, DEPT ELECT ENGN, MADRAS 600036, INDIA

来源：

PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON | 1974年 / 121卷 / 10期

关键词：

D O I：

10.1049/piee.1974.0253

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

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页码：1085 / 1086

页数：2

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