共 50 条
- [1] HIGH-SPEED PARALLEL CRC CIRCUITS IN VLSI [J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1992, 40 (04) : 653 - 657
- [3] An automatic clock tree design system for high-speed VLSI designs: Planar clock routing with the treatment of obstacles [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS, 1999, : 258 - 261
- [4] Automatic clock tree design system for high-speed VLSI designs: Planar clock routing with the treatment of obstacles [J]. Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 6
- [5] A practical repeater insertion method in high speed VLSI circuits [J]. 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 392 - 395
- [7] Interconnect mode conversion in high-speed VLSI circuits [J]. ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2004, : 265 - 270
- [8] Design of high-speed clock and data recovery circuits [J]. Analog Integrated Circuits and Signal Processing, 2007, 52 : 15 - 23
- [10] HIGH-SPEED CMOS I/O BUFFER CIRCUITS [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1992, E75C (04) : 569 - 571