Effective buffer insertion of clock tree for high-speed VLSI circuits

被引:0
|
作者
Wu, Bo [1 ]
Sherwani, Naveed [1 ]
机构
[1] Western Michigan Univ, Kalamazoo, United States
关键词
Integrated Circuits; VLSI;
D O I
10.1016/0026-2692(92)90026-W
中图分类号
学科分类号
摘要
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页码:291 / 300
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