Syntax checker for synthesizable subset of VHDL expressions

被引：0
|
作者：
Zhou, Y.X. [1 ]
Cao, W. [1 ]
Lin, Z.H. [1 ]
机构：
[1] VLSI Res. Inst., Shanghai Jiaotong Univ., Shanghai 200030, China
来源：
Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University | 2001年 / 35卷 / 02期
关键词：
Electron design - Electron design automatical - Syntax analysis - VHDL;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
(Edited Abstract)
引用
收藏
页码：216 / 218
相关论文
共 50 条
  • [31] A model-driven development approach to mapping UML state diagrams to synthesizable VHDL
    Wood, Stephen K.
    Akehurst, David H.
    Uzenkov, Oleg
    Howells, W. Gareth J.
    McDonald-Maier, Klaus D.
    IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (10) : 1357 - 1371
  • [32] A synthesizable VHDL model of the exact solution for three-dimensional hyperbolic positioning system
    Bucher, R
    Misra, D
    VLSI DESIGN, 2002, 15 (02) : 507 - 520
  • [33] VHDL and Verilog fundamentals - Expressions, operands, and operators
    Smith, DJ
    EDN, 1997, 42 (08) : 207 - &
  • [34] The maximal VHDL subset with a cycle-level abstraction
    Baker, WC
    Newton, AR
    EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS, 1996, : 470 - 475
  • [35] A FORMALIZATION OF A SUBSET OF VHDL IN THE BOYER-MOORE LOGIC
    RUSSINOFF, DM
    FORMAL METHODS IN SYSTEM DESIGN, 1995, 7 (1-2) : 7 - 25
  • [36] The syntax and semantics of vectorial expressions in Spanish
    Gonzalez Lopez, Laura
    VERBA-ANUARIO GALEGO DE FILOLOXIA, 2018, 45 : 39 - 65
  • [37] UNIFORM SYNTAX FOR TYPE EXPRESSIONS AND DECLARATORS
    SETHI, R
    SOFTWARE-PRACTICE & EXPERIENCE, 1981, 11 (06): : 623 - 628
  • [38] A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration
    Dasygenis, Minas
    2014 9TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2014), 2014,
  • [39] Fast prototyping based on generic and synthesizable VHDL models a case study: Punctured Viterbi decoders
    Deltoso, C
    Joanblanq, C
    Cand, M
    Senn, P
    SEVENTH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE, 1996, : 158 - 163
  • [40] An algorithm for the direct conversion of Boolean expressions into VHDL code
    Sirakoulis, Georgios Ch.
    Computational Methods in Circuits and Systems Applications, 2003, : 29 - 33
12345