Syntax checker for synthesizable subset of VHDL expressions

被引：0
|
作者：
Zhou, Y.X. [1 ]
Cao, W. [1 ]
Lin, Z.H. [1 ]
机构：
[1] VLSI Res. Inst., Shanghai Jiaotong Univ., Shanghai 200030, China
来源：
Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University | 2001年 / 35卷 / 02期
关键词：
Electron design - Electron design automatical - Syntax analysis - VHDL;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
(Edited Abstract)
引用
收藏
页码：216 / 218
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