Novel field reduction structure at tip of electrode fingers for low on-resistance high-voltage power double-diffused metal-oxide-semiconductor field-effect transistors

In this paper we report on a low on-resistance and high-voltage power double-diffused metal-oxide-semiconductor field-effect transistor (DMOSFET) with a newly proposed interdigitated form for power ICs, which is fabricated by a cost-effective standard complementary metal-oxide-semiconductor (CMOS) process. The basic structure with an extended p-base has a highly doped drift region. In an interdigitated form for high-current applications, the widely spread depletion layer from the drain side eliminates electric field concentration at the tip of the drain fingers. As for the tip of the source fingers, although the radius of curvature is only 15 μm, the newly proposed structure with a remainder p-substrate realizes a considerable decrease in electric field by the charge sharing effect. This structure realizes unlimited breakdown voltage at the corner. As a result of this technology, a 700 V power DMOSFET achieves more than 20% reduction of specific on-resistance.