共 50 条
- [31] The study of contact hole for 65nm node with KrF PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XIII, PTS 1 AND 2, 2006, 6283
- [32] On the interaction of ESD, NBTI and HCI in 65nm technology 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 17 - +
- [34] Designing for power, a 65nm lead microprocessor example 10TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS, 2006, : 163 - +
- [35] Multi-bit upsets in 65nm SOISRAMS 2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 195 - +
- [37] A Compact 67 GHz Oscillator in 65nm CMOS 2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2015,
- [38] 65nm Poly Gate Etch Challenges and Solutions 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1158 - 1161
- [39] 65nm CMOS technology for low power applications IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 69 - 72
- [40] Microeconomics of overlay control at the 65nm technology node 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2003, : 103 - 106