Processor subsystem interconnect architecture for a large symmetric multiprocessing system

被引:0
|
作者
Mak, Pak-Kin [1 ]
Strait, Gary E. [1 ]
Blake, Michael A. [1 ]
Kark, Kevin W. [1 ]
Papazova, Vesselina K. [1 ]
Seigler, A.E. [1 ]
Van Huben, Gary A. [1 ]
Wang, Liyong [1 ]
Wellwood, George C. [1 ]
机构
[1] IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, NY 12601, United States
来源
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:323 / 337
相关论文
共 50 条
  • [31] Heterogeneous architecture models for interconnect-motivated system design
    Chai, SM
    Taha, TM
    Wills, DS
    Meindl, JD
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (06) : 660 - 670
  • [32] SYSTEM ARCHITECTURE OF A MULTITASKING DIGITAL IMAGE-PROCESSOR
    PENDERGRASS, RA
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1983, 435 : 158 - 164
  • [33] THE ARCHITECTURE OF A MULTI-VECTOR PROCESSOR SYSTEM, VPP
    INOUE, A
    MAEDA, A
    PARALLEL COMPUTING, 1988, 8 (1-3) : 185 - 193
  • [34] Modeling of Processor Datapaths with VLIW Architecture at the System Level
    Tarasov, Ilya
    Kazantseva, Larisa
    Daeva, Sofia
    HIGH-PERFORMANCE COMPUTING SYSTEMS AND TECHNOLOGIES IN SCIENTIFIC RESEARCH, AUTOMATION OF CONTROL AND PRODUCTION, 2022, 1526 : 3 - 12
  • [35] THE ARCHITECTURE OF THE SURE-SYSTEM-2000 COMMUNICATIONS PROCESSOR
    KABEMOTO, A
    YOSHIDA, H
    IEEE MICRO, 1991, 11 (04) : 28 - &
  • [36] SYSTEM ARCHITECTURE OF VICOM DIGITAL IMAGE-PROCESSOR
    PRATT, WK
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1981, 301 : 78 - 82
  • [37] A System Architecture, Processor, and Communication Protocol for Secure Implants
    Strydis, Christos
    Seepers, Robert M.
    Peris-Lopez, Pedro
    Siskos, Dimitrios
    Sourdis, Ioannis
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2013, 10 (04)
  • [38] A control system processor architecture for complex LTI controllers
    Goodall, R
    Jones, S
    Cumplido-Parra, R
    Mitchell, F
    Bateman, S
    ALGORITHMS AND ARCHITECTURES FOR REAL-TIME CONTROL 2000, 2000, : 175 - 180
  • [39] Novel Graph Processor Architecture, Prototype System, and Results
    Song, William S.
    Gleyzer, Vitaliy
    Lomakin, Alexei
    Kepner, Jeremy
    2016 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2016,
  • [40] A Software Transactional Memory System for an Asymmetric Processor Architecture
    Goldstein, Felipe
    Baldassin, Alexandro
    Centoducatte, Paulo
    Azevedo, Rodolfo
    Garcia, Leonardo A. G.
    20TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS, 2008, : 175 - +