LOGIC DESIGN OF TERNARY LOGIC NETWORKS.

被引:0
|
作者
Tayama, Norio
机构
关键词
D O I
暂无
中图分类号
学科分类号
摘要
MATHEMATICAL TECHNIQUES
引用
收藏
页码:13 / 22
相关论文
共 50 条
  • [31] VALUE OF TERNARY LOGIC
    YOUNG, KJ
    COMPUTER JOURNAL, 1975, 18 (04): : 381 - 381
  • [32] TERNARY MAJORITY LOGIC
    VARSHAVS.VI
    AUTOMATION AND REMOTE CONTROL, 1964, 25 (05) : 612 - &
  • [34] An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS
    Ko, JongHyun
    Park, KwanWoo
    Yong, Suhyeong
    Jeong, TaeGam
    Kim, Tae Hak
    Song, Taigon
    2021 IEEE 51ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2021), 2021, : 189 - 194
  • [35] MEANINGFUL SPECIAL CLASSES OF TERNARY LOGIC FUNCTIONS - REGULAR TERNARY LOGIC FUNCTIONS AND TERNARY MAJORITY FUNCTIONS
    YAMAMOTO, Y
    MUKAIDONO, M
    IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (07) : 799 - 806
  • [36] Optimal alarm logic design for process networks
    Chang, CT
    Tsai, CS
    THIRD INTERNATIONAL CONFERENCE ON FOUNDATIONS OF COMPUTER-AIDED PROCESS OPERATIONS, 1998, 94 (320): : 345 - 350
  • [37] Design neural networks based fuzzy logic
    Yang, YP
    Xu, XM
    Zhang, WY
    FUZZY SETS AND SYSTEMS, 2000, 114 (02) : 325 - 328
  • [38] DESIGN OF LOGIC NETWORKS WITH REDUNDANCY AND TESTABILITY CONSIDERATIONS
    DANDAPANI, R
    REDDY, SM
    IEEE TRANSACTIONS ON COMPUTERS, 1974, C 23 (11) : 1139 - 1149
  • [39] Ternary logic gate and multiplier design based on binary memristor
    Wu J.
    Zhu Y.
    Zhong Y.
    Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/Journal of Huazhong University of Science and Technology (Natural Science Edition), 2024, 52 (03): : 14 - 19and27
  • [40] Design of Various Logic Gates in Neural Networks
    Yellamraju, Suryateja
    Kumari, Swati
    Girolkar, Suraj
    Chourasia, Surabhi
    Tete, A. D.
    2013 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2013,