Performance analysis of a new CMOS output buffer

被引：0
|
作者：
机构：
[1] Mahendranath, B.
[2] Srinivasulu, Avireni
来源：
| 1600年 / IEEE Computer Society卷
关键词：
Switching;
D O I：
10.1109/ICCPCT.2013.6529041
中图分类号：
TN3 [半导体技术]; TN4 [微电子学、集成电路（IC）];
学科分类号：
0805 ; 080501 ; 080502 ; 080903 ; 1401 ;
摘要：
A new CMOS output buffer with low switching noise and load adaptability is presented in this paper. The proposed circuit consists of two stages; first stage is set to reduce switching noise, static power dissipation and also output ringing. The second stage involves enough speed and full dynamic range. The performance of the proposed circuit is examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results have confirmed that the proposed output buffer can reduce propagation delay compared with the previous designs. The topology reports low sensitivities and has features suitable for VLSI implementation. © 2013 IEEE.
引用
收藏
相关论文
共 50 条
  • [1] Performance Analysis of a New CMOS Output Buffer
    Mahendranath, B.
    Srinivasulu, Avireni
    PROCEEDINGS OF 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2013), 2013, : 752 - 755
  • [2] Design of a new CMOS output buffer with low switching noise
    Yang, L
    Yuan, JS
    ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 131 - 134
  • [3] A reduced output ringing CMOS buffer
    Bartolini, Michele
    Pulici, Paolo
    Stoppino, Pier Paolo
    Campardo, Giovanni
    Vanalli, Gian Pietro
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (02) : 102 - 106
  • [4] A high performance, high voltage output buffer in a low voltage CMOS process
    Chauhan, R
    Rajagopal, K
    Menezes, V
    Roopashree, HM
    Jacob, SK
    CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, : 227 - 230
  • [5] CMOS DATA OUTPUT BUFFER FOR INTEGRATED MEMORIES
    MALOBERTI, F
    MARCHESI, G
    TORELLI, G
    ELECTRONICS LETTERS, 1992, 28 (21) : 1946 - 1947
  • [6] A new high-frequency very low output-impedance CMOS buffer
    Manetakis, K
    Toumazou, C
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 1, 1996, : 485 - 488
  • [7] Transient behavioral SPICE modeling of CMOS output buffer
    Huang, Chun-Xing
    Zhu, Xiao-Hua
    Nanjing Li Gong Daxue Xuebao/Journal of Nanjing University of Science and Technology, 2005, 29 (01): : 43 - 45
  • [8] CMOS SUBNANOSECOND TRUE-ECL OUTPUT BUFFER
    SCHUMACHER, HJ
    DIKKEN, J
    SEEVINCK, E
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) : 150 - 154
  • [9] LOW-OUTPUT-IMPEDANCE CMOS VOLTAGE BUFFER
    MUCHA, I
    ELECTRONICS LETTERS, 1992, 28 (22) : 2071 - 2072
  • [10] Nonlinear performance of the CMOS buffer stages
    Abuelma'atti, MT
    Al-Zaher, HA
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1999, 86 (01) : 43 - 53
12345