Efficient implementation of the CCSDS 122.0-B-1 compression standard on a space-qualified field programmable gate array

被引：0

作者：

机构：

[1] Li, Li

[2] Zhou, Gang

[3] Fiethe, Björn

[4] Michalik, Harald

[5] Osterloh, Björn

来源：

| 1600年 / SPIE卷 / 07期

关键词：

High speed cameras - Signal encoding - Space flight - Logic gates - Discrete wavelet transforms - Image compression;

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摘要：

Journal article (JA)

引用

共 29 条

[21] Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor
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[22] HARDWARE IMPLEMENTATION OF THE CCSDS 123.0-B-1 LOSSLESS MULTISPECTRAL AND HYPERSPECTRAL IMAGE COMPRESSION STANDARD BY MEANS OF HIGH LEVEL SYNTHESIS TOOLS
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[23] Implementation of a high speed four transmitter space-time encoder using field programmable gate array and parallel digital signal processors
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[26] Implementation of fast independent component analysis on field-programmable gate array for resolving the slot collision issue in the space-based automatic identification system
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[27] Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array
Green, PJ
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DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, 2006, : 89 - +
[28] Nonvolatile field-programmable gate array using 2-transistor-1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic
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JAPANESE JOURNAL OF APPLIED PHYSICS, 2015, 54 (04)
[29] An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec
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