A networks-on-chip emulation/verification framework

被引：0
|
作者：
Liu P. [1 ]
Liu Y. [1 ]
Xia B. [1 ]
Xiang C. [1 ]
Wang X. [1 ]
Wu K. [1 ]
Wang W. [1 ]
Yao Q. [1 ]
机构：
[1] Department of Information Science and Electronic Engineering, Zhejiang University, Yuquan Campus
来源：
International Journal of High Performance Systems Architecture | 2011年 / 3卷 / 01期
关键词：
Emulation; Field programmable gate array; FPGA; Networks-on-chip; NoC; On-chip interconnection; Router;
D O I：
10.1504/IJHPSA.2011.038053
中图分类号：
学科分类号：
摘要：
The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of field programmable gate array. Copyright © 2011 Inderscience Enterprises Ltd.
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页码：2 / 11
页数：9
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