VLSI design of BCH decoder in NAND flash controller

被引:0
|
作者
机构
[1] Zheng, Zhaoxia
[2] Ding, Mingpeng
[3] Zhong, Jianfu
[4] Li, Jicheng
来源
Zheng, Z. (zxzheng@hust.edu.cn) | 1600年 / Huazhong University of Science and Technology卷 / 42期
关键词
D O I
10.13245/j.hust.140120
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [31] Design of a VLSI hardware PET decoder
    Ascia, G
    Catania, V
    Ficili, G
    [J]. TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 253 - 256
  • [32] Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory
    Shao, Wei
    Sha, Jin
    Zhang, Chuan
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (08) : 1014 - 1018
  • [33] High-efficient superblock flash translation layer for NAND flash controller
    Zhang, Peiyong
    Tang, Huanjie
    [J]. ELECTRONICS LETTERS, 2020, 56 (06) : 278 - +
  • [34] Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices
    Nabipour, Saeideh
    Javidan, Javad
    Drechsler, Rolf
    [J]. Memories - Materials, Devices, Circuits and Systems, 2024, 7
  • [35] 基于BCH码的NAND Flash纠错算法设计与实现
    陈昭林
    张晋宁
    沈辉
    [J]. 电子测量技术, 2017, 40 (03) : 127 - 132
  • [36] Serial Quasi-Primitive BC-BCH Codes for NAND Flash Memories
    Kim, Daesung
    Ha, Jeongseok
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2016, : 404 - 409
  • [37] A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
    Lin, Yi-Min
    Yang, Chi-Heng
    Hsu, Chih-Hsiang
    Chang, Hsie-Chia
    Lee, Chen-Yi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (10) : 682 - 686
  • [38] 基于Nand Flash的BCH校验方法设计与实现
    焦新泉
    武慧军
    单彦虎
    秦菲
    [J]. 电测与仪表, 2017, 54 (22) : 59 - 64
  • [39] A Novel Optimization Algorithm for Chien Search of BCH Codes in NAND Flash Memory Devices
    Zhang, Meng
    Wu, Fei
    Xie, Changsheng
    Zhou, You
    Zou, Kai
    [J]. PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON NETWORKING, ARCHITECTURE AND STORAGE (NAS), 2015, : 106 - 111
  • [40] Verification and Simulation of New Designed NAND Flash Memory Controller
    Agarwal, Koushel
    Magraiya, Vijay Kumar
    Saxena, Anil Kishore
    [J]. 2013 INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT 2013), 2013, : 762 - 766